library verilog;
use verilog.vl_types.all;
entity clok_div is
    port(
        clk_1kHz        : in     vl_logic;
        rst             : in     vl_logic;
        clk_4Hz         : out    vl_logic;
        clk_1Hz         : out    vl_logic;
        clk_10Hz        : out    vl_logic
    );
end clok_div;
